library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;


entity checker is
  generic (N     :     integer := 32);
  port( data_in  : in  std_logic_vector (N-1 downto 0);
        cmp_need : in  std_logic_vector (2 downto 0);
        sel      : out std_logic
        );
end checker;

architecture Behavioral of checker is

  component comparator is
                         generic (N :     integer := 32);
                       port( data_0 : in  std_logic_vector (N-1 downto 0);
                             data_1 : in  std_logic_vector (N-1 downto 0);
                             CMP_LT : out std_logic;
                             CMP_EQ : out std_logic;
                             CMP_GT : out std_logic
                             );
  end component;

  signal l, g, e : std_logic;
  signal zero    : std_logic_vector(N-1 downto 0);
begin

  zero <= (others => '0');

  COMPARE : comparator generic map(N) port  --compare data_in with 0
    map(data_in, zero, l, e, g);

process (data_in, cmp_need, l, e, g)
begin
	case cmp_need is
		when "010"  =>			-- ==
			sel <= e and (not l and not g);
		when "101"  =>			-- /=
			sel <= (l or g) and not e;
		when "100"  =>			--  < 
			sel <= l and (not e and not g);
		when "001"  =>			--  >
			sel <= g and (not e and not l);
		when "110"  =>			--  <= 
			sel <= (l or e) and g;
		when "011"  =>			--  >=
			sel <= (e or g) and not l;
		when "111"  =>			-- always true
			sel   <= '1';
		when others =>			-- always false
			sel   <= '0';
	end case;
end process;

end Behavioral;

